In this work the design of one combinational circuit in the form of Sum of Product (SOP) using Static & Dynamic CMOS method has been reported. The design has been carried out at 150nm channel length of MOS transistor. The functionality of the circuit has been clarified using the Tanner-SPICE software. Average power consumption, gate delay and power delay product (PDP) has been reported. The average power consumption and gate delay has been reported for the range of VDD from 0.5 V to 1.2 V. The comparative results of the circuit context to average power &gate delay of static CMOS and dynamic CMOS design have been presented. From the simulation results, it is found that the optimum value of PDP for the design using static and dynamic CMOS has been obtained at 0.8 V and 0.9 V respectively. The corresponding PDP values are 0.343 aJ and 0.502 aJ. Therefore, the work in this paper may be considered as prototype design for the application of high-speed & low-power VLSI circuits.